Finally…

0xb4560c45 sceSysregPllGetOutSelect
0xdca57573 sceSysregPllSetOutSelect

I’ve been trying to crack these 2 nids for awhile. These are used to get/set the PLL index that multiplies with the base frequency to change the PLL freq (to change cpu & bus freq). The index is as follows:

view plain
C:
  1. const float pll_table[0×10] =
  2. {
  3.     1/9.0,    // 0.1…
  4.     4/9.0,    // 0.4…
  5.     4/7.0,    // 0.571428…
  6.     6/9.0,    // 0.6…
  7.     4/5.0,    // 0.8
  8.     9/9.0,    // 1.0
  9.     0.0,
  10.     0.0,
  11.  
  12.     1/18.0,   // 0.05…
  13.     4/18.0,   // 0.2…
  14.     4/14.0,   // 0.285714…
  15.     6/18.0,   // 0.3…
  16.     4/10.0,   // 0.4
  17.     9/18.0,   // 0.5
  18.     0.0,
  19.     0.0
  20. };

Although the index is from 0-15, sceSysregPllSetOutSelect limits it to 0-5 only. The default is 3 (ie. 0.666666…). So default PLL freq is (multiplier*BASE_FREQ) * pll_table[index] = 9*37 * 0.66666 = 222MHz. To set to 333MHz just call sceSysregPllSetOutSelect(5) (which will also make the cpu freq 333MHz).

EDIT: For completeness, here’s what I had originally written about it: http://lan.st/showthread.php?t=854

This entry was posted on Wednesday, November 7th, 2007 at 4:29 pm and is filed under NID's. You can follow any responses to this entry through the RSS 2.0 feed. You can skip to the end and leave a response. Pinging is currently not allowed.

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